Ic card and ic card system

ABSTRACT

When data is transmitted from a main unit of an apparatus  11  to an IC card  12 , a clock signal is input to a clock input of FF 2 R through a path of (buffer CK 1 S→transmission path CLK→buffer CK 2 R). A data signal is output from FF 1 S in synchronization with a leading edge of the clock signal. The data signal is input to a data input of FF 2 R through a path of (buffer 10 1 S→transmission path DATA→buffer  102 R). Thereafter, the data signal is captured. When data is transmitted from the IC card  12  to the main body  11 , a clock signal is input to a clock input of FF 1 R through a path of (buffer CK 2 S→transmission path CLK→buffer CK 1 R). The data signal is output from FF 2 S in synchronization with a leading edge of the clock signal. The clock signal is input to a data input of FF 1 R through a path of (buffer  102 S→transmission path DATA→buffer  101 R). Thereafter, the data signal is captured.

TECHNICAL FIELD

[0001] The present invention relates to an IC card and an IC card systemthat has for example a flash memory and that is removable from a mainunit of a data processing apparatus.

BACKGROUND ART

[0002]FIG. 1 is a block diagram showing a data communicating methodperformed between a main unit of a conventional apparatus (hereinafterreferred to as main unit 1) and an IC card 2. To perform a datacommunication between the main unit 1 and the IC card 2, a clock signaland a data signal that is input and output in synchronization therewithare used. While the data signal is bi-directionally communicated betweenthe main unit 1 and the IC card 2, the clock signal is one-directionallycommunicated from the main unit 1 to the IC card 2.

[0003]FIG. 2 is a block diagram showing a detailed structure of thesystem shown in FIG. 1. In FIG. 2, reference characters FF1R, FF1S,FF2R, and FF2S represent flip-flops. Each of the flip-flops FF1R, FF1S,FF2R, and FF2S has a data input D and a data output Q. Referencecharacters 101R, 102R, and CLK1 represent input buffers. Referencecharacters 101S, 102S, and CLK0 represent output buffers. Referencecharacters 101S, 102S, 101R, and 102R are composed of tri-state buffers.The main unit 1 has a clock generator 3 that generates a clock signal.Reference characters 1DE and 2DE represent control signals. Referencecharacters DATA and CLK represent a data transmission path and a clocktransmission path disposed between the main unit 1 and the IC card 2,respectively.

[0004] First of all, the case that a data communication is performedfrom the main unit 1 to the IC card 2 will be described. The controlsignal 1DE causes the tri-state buffer 101S to be set to an outputenable state. The control signal 2DE causes the tri-state buffer 102S tobe set to an output high impedance state. Thus, data is transmitted fromthe flip-flop FF1S to the flip-flop FF2R. The clock signal is generatedby the clock generator 3 of the main unit 1. The clock signal is inputto the clock input of the flip-flop FF2R through a path of (outputbuffer CLK0→transmission path CLK→input buffer CLK1).

[0005] The data signal is output from the flip-flop FF1S insynchronization with a leading edge of the clock signal that is inputfrom the clock generator 3 to the clock input of the flip-flop FF1S. Thedata signal is input to the data input of the flip-flop FF2R through apath of (output buffer 101S→transmission path DATA→input buffer 102R).The data signal is captured in synchronization with a leading edge ofthe clock input of the flip-flop FF2R.

[0006] Next, the case that a data communication is performed from the ICcard 2 to the main unit 1 will be described. The control signal 1DEcauses the tri-state buffer. 101S to be set to an output high impedancestate. The control signal 2DE causes the tri-state buffer 102S to be setto an output enable state. Thus, a data transmission is performed fromthe flip-flop FF2S to the flip-flop FF1R. The clock signal is generatedby the clock generator 3 of the main unit 1. The clock signal is inputto the clock input of the flip-flop FF1R.

[0007] The data signal is output from the flip-flop FF2S insynchronization with a leading edge of the clock signal that is input tothe clock input of the flip-flop FF2S through a path of (clock generator3→output buffer CLK0→transmission path CLK→input buffer CLK1). The datasignal is input to the data input of the flip-flop FF1R through a pathof (output buffer 102S→transmission path DATA→input buffer 101R). Thedata signal is captured in synchronization with a leading edge of theclock input of the flip-flop FF1R.

[0008]FIG. 3 is a schematic diagram showing the structure of a systemthat performs a data communication from the IC card 2 to the main unit1. FIG. 4 is a timing chart showing the data communication performed bythe system shown in FIG. 3. Next, the system and timing chart of thedata communication performed thereby shown in FIGS. 3 and 4 will bedescribed.

[0009] As shown in FIG. 3, when the data communication is performed fromthe IC card 2 to the main unit 1, the data signal is transmitted fromthe flip-flop FF2S to the flip-flop FF1R. The clock signal that is inputto the flip-flop FF2S has a delay that is the sum of a delay due to theoutput buffer CLK0, a delay due to the transmission path CLK, and adelay due to the input buffer CLK1 against the clock signal that isinput to the flip-flop FF1R. The sum of the delays is denoted by clockdelay TD1.

[0010] A delay after a leading edge of the clock input of the flip-flopFF2S until the arrival of the clock signal to the data input of theflip-flop FF1R is the sum of a delay due to the flip-flop FF2S, a delaydue to the output buffer 102S, a delay due to the transmission pathDATA, and a delay of the input buffer 101R. The delay due to theflip-flop FF2S is denoted by data delay TD3. The sum of the delay due tothe tri-state buffer 102S, the delay due to the transmission path DATA,and the delay due to the input buffer 101R is denoted by data delay TD2.

[0011] The data that is output in synchronization with the clock inputof the flip-flop FF2S should arrive at the data input of the flip-flopFF1R by the next leading edge of the clock input of the flip-flop FF1R.However, since there are clock delay TD1 and data delays TD2 and TD3,the timing tolerance becomes insufficient as shown in FIG. 4. As aresult, although it is necessary to shorten the clock period for ahigher data communication, a clock period equal to or lower than (delayTD1+delay TD2+delay TD3) cannot be accomplished.

[0012] Therefor, an object of the present invention is to provide an ICcard and an IC card system that have a structure that allows thedifference between the delay time of the clock signal and the delay timeof the data signal to become zero so that a communication for data thatis output from the IC card can be performed at higher speed than beforeand a larger amount of data can be transmitted in a shorter time thanbefore.

DISCLOSURE OF THE INVENTION

[0013] The invention of claim 1 is an IC card removable from a main unitof an apparatus, the IC card having a data terminal and a clockterminal, a clock signal being capable of being received from the mainunit through the clock terminal, the clock signal being capable of beingtransmitted from the clock terminal to the main unit.

[0014] The invention of claim 4 is an IC card system composed of a mainunit of an apparatus and a removable IC card, the IC card systemcomprising:

[0015] interface means including a data transmission path and a clocktransmission path,

[0016] wherein the interface means is configured:

[0017] to transmit a first clock signal from the main unit to the ICcard through the clock transmission path and transmit data from the mainunit to the IC card in synchronization with the first clock signalthrough the data transmission path and,

[0018] to transmit a second clock signal from the IC card to the mainunit through the clock transmission path and transmit data from the ICcard to the main unit through the data transmission path insynchronization with the second clock signal.

[0019] According to the present invention, when data is transmitted fromthe IC card to the main unit, the clock signal is bi-directionallycommunicated. Both the data signal and the clock signal are transmittedfrom the IC card to the main unit. In addition, the difference betweenthe delay time of the data signal and the delay time of the clock signalbecomes zero. As a result, the clock period can be more shortened andthe communication can be performed at higher speed than before.

BRIEF DESCRIPTION OF DRAWINGS

[0020]FIG. 1 is a block diagram showing a data communicating methodperformed between a conventional main unit and an IC card;

[0021]FIG. 2 is a schematic diagram showing the detailed structure of asystem that performs the data communicating method shown in FIG. 1;

[0022]FIG. 3 is a schematic diagram showing the structure of a systemthat performs a data communication from an IC card to a main unit;

[0023]FIG. 4 is a timing chart for explaining the data communicationperformed by the system shown in FIG. 3;

[0024]FIG. 5 is a block diagram showing an example of an IC card systemaccording to the present invention;

[0025]FIG. 6 is a timing chart for explaining the IC card system;

[0026]FIG. 7 is a timing chart for explaining the IC card system;

[0027]FIG. 8 is a perspective view showing an example of the shape ofthe IC card according to the present invention;

[0028]FIG. 9 is a schematic diagram viewed from an H direction of the ICcard;

[0029]FIG. 10 is a schematic diagram viewed from an I direction of theIC card shown in FIG. 8;

[0030]FIG. 11 is a block diagram showing an outlined structure of the ICcard system according to the present invention;

[0031]FIG. 12 is a block diagram showing an embodiment of the presentinvention;

[0032]FIG. 13 is a block diagram for explaining a data communicationperformed from the IC card to the main unit according to the embodimentof the present invention;

[0033]FIG. 14 is a timing chart for explaining the data communicationshown in FIG. 13;

[0034]FIG. 15 is a block diagram of another embodiment of the presentinvention; and

[0035]FIG. 16 is a block diagram for explaining a data communicationperformed from an IC card to a main unit according to the otherembodiment of the present invention.

BEST MODES FOR CARRYING OUT THE INVENTION

[0036] Next, with reference to the accompanying drawings, embodiments ofthe present invention will be described. First of all, an example of anIC card (memory apparatus) according to the present invention will bedescribed.

[0037]FIG. 5 shows the structure of a system composed of a main unit 21and an IC card 26. The main unit 21 has a data processing portion 22, aregister 23, a host side serial interface circuit 24, and a host sidecontroller 25. The IC card 26 is a storage medium having a card shapedappearance. The IC card 26 is used as an external storing unit connectedto the main unit 21. The IC card 26 has a memory 27, a register 28, acard side serial interface circuit 29, and a card side controller 30.

[0038] The data processing portion 22 of the main unit 21 reads datafrom the IC card 26 and performs various processes therefor andgenerates data to be written to the IC card 26. In other words, the dataprocessing portion 22 is a data processing circuit used in a computerapparatus that uses the IC card 26, used in a recording and reproducingapparatus for a digital audio signal, or used in an audio visualapparatus such as a camera apparatus.

[0039] The register 23 is a buffer for the data processing portion 22and the host side serial interface circuit 24. In other words, when themain unit 21 supplies data from the data processing portion 22 to thehost side serial interface circuit 24, the main unit 21 temporarilystores the data to the register 23 and then supplies the data to thehost side serial interface circuit 24. Likewise, when the main unit 21supplies data from the host side serial interface circuit 24 to the dataprocessing portion 22, the main unit 21 temporarily stores the data tothe register 23 and then supplies the data to the data processingportion 22.

[0040] The host side serial interface circuit 24 converts data suppliedfrom the data processing portion 22 through the register 23 and acommand supplied from the host side controller 25 into a serial signaland supplies the serial signal to the IC card 26. In addition, the hostside serial interface circuit 24 converts the data and command of theserial signal supplied from the IC card 26 into parallel signals andsupplies the parallel signals to the data processing portion 22 and thehost side controller 25.

[0041] In addition, the host side serial interface circuit 24 supplies asynchronous signal (CLK) and so forth for various types of data andcommands to the IC card 26. In addition, the host side serial interfacecircuit 24 obtains from the IC card 26 a status signal that representsthe operating state thereof.

[0042] The host side controller 25 controls a data processing operationof the data processing portion 22 and a transmitting operation of thehost side serial interface circuit 24 for various types of data. Inaddition, the host side controller 25 supplies to the IC card 26 acommand as a control instruction therefor through the register 28.

[0043] On the other hand, the memory 27 of the IC card 26 is composed offor example a flash memory. The memory 27 stores data supplied from thedata processing portion 22.

[0044] The register 28 is a buffer for the memory 27 and the card sideserial interface circuit 29. In other words, when data supplied from themain unit 21 is written to the memory 27, the register 23 temporarilystores the data and then supplies the data to the memory 27. Likewise,when the main unit 21 reads data from the memory 27, the main unit 21temporarily stores the data to the register 23 and then supplies thedata to the card side serial interface circuit 29. In other words, theregister 28 is a circuit that performs a so-called page buffer functionor the like of the flash memory.

[0045] The card side serial interface circuit 29 converts data of aparallel signal supplied from the memory 27 and a command supplied fromthe card side controller 30 into a serial signal under the control ofthe card side controller 30 and supplies the serial signal to the mainunit 21. In addition, the card side serial interface circuit 29 convertsdata and a command of the serial signal supplied from the main unit 21into parallel signals and supplies the parallel signals to the memory 27and the card side controller 30.

[0046] In addition, the card side serial interface circuit 29 supplies asynchronous signal (CLK) and so forth for various types of data and acommand to the main unit 21. In addition, the card side serial interfacecircuit 29 supplies a status signal to the main unit 21.

[0047] The card side controller 30 controls a data storing operation, adata reading operation, a data erasing operation, and so forth of thememory 27 corresponding to commands and so forth supplied from the mainunit 21. In addition, the card side controller 30 controls atransmitting operation of the card side serial interface circuit 29 forvarious types of data. The host side controller 25 controls the supplyfor the status signal to the IC card 26.

[0048] The data transmission between the main unit 21 and the IC card 26is performed through transmission lines disposed between the host sideserial interface circuit 24 and the card side serial interface circuit29.

[0049] Three signal lines that are a CLK line 31, a control line 32, anda DT line 33 are disposed between the host side serial interface circuit24 of the main unit 21 and the card side serial interface circuit 29 ofthe IC card 26.

[0050] Main data that is data processed by the data processing portion22 and written to the memory 27 and data that is read from the memory 27to the data processing portion 22 is transmitted through the DT line 33.In addition, a command as a control instruction supplied from the mainunit 21 to the IC card 26 and a command supplied from the IC card 26 tothe main unit 21 are transmitted through the DT line 33. In other words,the main data and command as a serial signal are bi-directionallytransmitted through the DT line 33.

[0051] A resistor 33 a is connected to the DT line 33. One end of theresistor 33 a is grounded. The resistor 33 a is a so-called pull downresistor. While a signal is not being transmitted and received betweenthe host side serial interface circuit 24 and the card side serialinterface circuit 29 through the DT line 33, the signal level of the DTline 33 is low. In other words, while a signal is not being transmittedand received through the DT line 33, the signal level of the DT line 33is constant that depends on the resistance and so forth of the resistor33 a.

[0052] In this example, for the resistor 33 a, a so-called pull downresistor is used. While a signal is not being transmitted and receivedthrough the DT line 33, the signal level of the DT line 33 is low. Itshould be noted that for the resistor 33 a, a so-called pull up resistorcan be used. In this case, while a signal is being not transmitted andreceived through the DT line 33, the signal level of the DT line 33 ishigh. A clock signal is bi-directionally transmitted between the mainunit 21 and the IC card 26 through the CLK line 31.

[0053] A control signal is supplied from the main unit 21 to the IC card26 through the control line 32.

[0054] While the control signal is being supplied (for example, whilethe signal level of the control signal is high), the main data andcommand are transmitted.

[0055] In addition to the main data and command, a status signal thatrepresents the operating state of the IC card 26 is supplied from the ICcard 26 to the main unit 21 through the DT line 33. The status signal issupplied from the IC card 26 while the main data and command are notbeing transmitted through the DT line 33 (namely, while the controlsignal is not being supplied, for example while the signal level islow). The status signal includes a busy signal that represents that theIC card 26 is performing a process. When the IC card 26 is performing awriting process and the main unit 21 is prohibited from accessing the ICcard 26, the busy signal is supplied from the IC card 26 to the mainunit 21. The status signal also includes an interrupt signal thatrepresents that the IC card 26 requests the main unit 21 to perform aparticular operation. When the IC card 26 requests the main unit 21 toexecute an interrupt instruction, the IC card 26 supplies the interruptsignal to the main unit 21. It should be noted that the busy signal andinterrupt signal are just examples. In other words, as long as thestatus signal represents an operating state of the IC card 26, thestatus signal may be any signal.

[0056]FIG. 6 shows a timing at which data is read from the IC card 26.While no data is being transmitted and received between the main unit 21and the IC card 26, the signal level of the control line 32 is low. Thisstate is referred to as state 0 (initial state). At timing t31, the mainunit 21 changes the signal level of the control line 32 to high. As aresult, the state 0 is changed to state 1.

[0057] When the signal level of the control line 32 becomes high, the ICcard 26 detects that the state 0 has been changed to the state 1. In thestate 1, a read command is transmitted from the main unit 21 to the ICcard 26 through the DT line 33. The IC card 26 receives the readcommand. The read command is a protocol command referred to as serialinterface TPC. As will be described later, the protocol commanddesignates the content to be communicated and the data length of datathat is followed thereby.

[0058] After the command has been transmitted at timing t32, the signallevel of the control line 32 is changed from high to low. As a result,the state 1 is changed to state 2. In the state 2, the IC card 26performs a process designated by a read command (in reality, a processfor reading data from the memory 27 corresponding to an addressdesignated by the read command). While the IC card 26 is performing theprocess, a busy signal (in high level) is transmitted to the main unit21 through the DT line 33.

[0059] After data has been read from the memory 27 at timing t33, theoutput of the busy signal is stopped. The output of a ready signal (inlow level) that represents that the IC card 26 is ready for transmittingdata to the main unit 21 is started.

[0060] When the main unit 21 receives the ready signal from the IC card26, the main unit 21 knows that the IC card 26 is ready for the processcorresponding to the read command. At timing t34, the main unit 21changes the signal level of the control line 32 to high. In other words,the state 2 is changed to the state 3.

[0061] In the state 3, the IC card 26 outputs the data that has beenread to the register 28 in the state 2 to the main unit 21 through theDT line 33. After the data that had been read has been transmitted attiming t35, the main unit 21 stops transmitting the clock signal. Inaddition, the main unit 21 changes the signal level of the status linefrom high to low. As a result, the state 3 is changed to the initialstate (state 0).

[0062] When some interrupt process is required due to a change of theinternal state of the IC card 26, at timing t36, the IC card 26 suppliesthe interrupt signal that represents an interrupt to the data processingapparatus through the DT line 33 in the state 0. The main unit 21 isdesignated to know that when a signal is supplied from the IC card 26through the DT line 33 in the state 0, the signal is an interruptsignal. When the main unit 21 receives the interrupt signal, the mainunit 21 performs a predetermined process corresponding to the interruptsignal.

[0063]FIG. 7 is a timing chart showing the case that data is written tothe memory 27 of the IC card 26. In the initial state (state 0), nosignal is transmitted through the CLK line 31. At timing t41, the mainunit 21 changes the signal level of the control line 32 from low tohigh. As a result, the initial state is changed to the state 1. In thestate 1, a write command is transmitted through the DT line 33. In thestate 1, the IC card 26 is ready for obtaining a command. At timing t41,a command is transmitted to the IC card 26 through the DT line 33. TheIC card 26 obtains the write command.

[0064] After the write command has been transmitted at timing t42, themain unit 21 changes the signal level of the control line 32 from highto low. As a result, the state 1 is changed to the state 2. In the state2, the main unit 21 transmits write data to the IC card 26 through theDT line 33. In the IC card 26, the received write data is stored in theregister 28.

[0065] After the write data has been transmitted at step t43, the mainunit 21 changes the signal level of the control line 32 from low tohigh. As a result, the state 2 is changed to the state 3. In the state3, the IC card 26 performs a process for writing the write data to thememory 27. In the state 3, the IC card 26 transmits a busy signal (inhigh level) to the main unit 21 through the DT line 33. Since the mainunit 21 has transmitted the write command and the current state is thestate 3, the main-unit 21 knows that the signal transmitted from the ICcard 26 is a status signal.

[0066] After the IC card 26 has performed the writing process for thewrite data at timing t44, the IC card 26 stops outputting the busysignal and transmits the ready signal (in low level) to the main unit21. When the main unit 21 receives the ready signal, the main unit 21determines that the IC card 26 has completed the writing processcorresponding to the write command and stops transmitting the clocksignal to the IC card 26. At timing t45, the main unit 21 changes thesignal level of the control line 32 from high to low. As a result, thestate 3 is returned to the state 0 (initial state).

[0067] When the main unit 21 has received a signal in high level fromthe IC card 26 through the DT line 33 in the state 0, the main unit 21knows that this signal is an interrupt signal. The main unit 21 performsa predetermined process corresponding to the received interrupt signal.For example, when the IC card 26 is removed from the main unit 21, theIC card 26 generates the interrupt signal.

[0068] Besides the forgoing reading operation and writing operation, inthe state 1, a command is transmitted; in the state 2 preceded thereby,data corresponding to the command is transmitted.

[0069]FIG. 8 shows an appearance of the IC card 41. FIG. 9 shows the ICcard 41 viewed from an H direction of FIG. 8. FIG. 10 shows the IC card41 viewed from an I direction of FIG. 8. The IC card 41 has a nearlyrectangular plane shape. The IC card 41 has a first side plane 42 and asecond side plane 43. At both edge portions of the first side plane 42,mounting notch portions 44 a and 44 b are formed, respectively. As shownin FIG. 9, at both edge portions of the second side plane 43, mountingnotch portions 44 c and 44 d are formed, respectively.

[0070] The present invention applied for the forgoing removable IC cardand main unit. For example, the present invention is applied for a datacommunication performed between the host side serial interface circuit24 shown in FIG. 5 and the card side serial interface circuit 29. FIG.11 shows an IC card system according to the present invention. Toperform a data communication between a main unit 11 and an IC card 12, aclock signal and a data signal that is input and output insynchronization therewith are used. Not only the data signal, but theclock signal is bi-directionally communicated.

[0071]FIG. 12 shows an embodiment of the present invention. In FIG. 12,reference characters FF1R, FF1S, FF2R, and FF2S represent flip-flops.Each of the flip-flops FF1R, FF1S, FF2R, and FF2S has a data input D anda data output Q. Reference characters 101R, 102R, CK1R, and CK2Rrepresent input buffers. Reference characters 101S, 102S, CK1S, and CK2Srepresent output buffers. The output buffers 101S, 102S, CK1S, and CK2Sare composed of tri-state buffers. The main unit 11 has a clockgenerator 13. The IC card 12 has a clock generator 14. Referencecharacters 1DE and 2DE represent control signals. Reference charactersDATA and CLK represent transmission paths disposed between the main unit11 and the IC card 12.

[0072] First of all, the case that data is transmitted from the mainunit 11 to the IC card 12 will be described. The control signal 1DEcauses the tri-state buffers 101S and CK1S to be set to an output enablestate. The control signal 2DE causes the tri-state buffers 102S and CK2Sto be set to an output high impedance state. As a result, data istransmitted from the flip-flop FF1S to the flip-flop FF2R. A clocksignal is generated by the clock generator 13 of the main unit 11. Theclock signal is input to the clock input of the flip-flop FF2R through apath of (output buffer CK1S→transmission path CLK→input buffer CK2R).

[0073] A data signal is output from the flip-flop FF1S insynchronization with a leading edge of the clock signal that is inputfrom the clock generator 13 to the clock input of the flip-flop FF1S.The data signal is input to the data input of the flip-flop FF2R througha path of (output buffer 101S→transmission path DATA→input buffer 102R).The data signal is captured in synchronization with a leading edge ofthe clock input of the flip-flop FF2R.

[0074] Next, the case that data is transmitted from the IC card 12 tothe main unit 11 will be described. The control signal 1DE causes thetri-state buffers 101S and CK1S to be set to an output high impedancestate. The control signal 2DE causes the tri-state buffers 102S and CK2Sto be set to an output enable state. As a result, data is transmittedfrom the flip-flop FF2S to the flip-flop FF1R. A clock signal isgenerated by the clock generator 14 of the IC card 12. The clock signalis input to the clock input of the flip-flop FF1R through a path of(output buffer CK2S→transmission path CLK→input buffer CK1R).

[0075] A data signal is output from the flip-flop FF2S insynchronization with a leading edge of the clock signal that is inputfrom the clock generator 14 to the clock input of the flip-flop FF2S.The data signal is input to the data input of the flip-flop FF1R througha path of (output buffer 102S→transmission path DATA→input buffer 101R)and captured in synchronization with a leading edge of the clock inputof the flip-flop FF1R.

[0076]FIG. 13 is a schematic diagram showing the structure of the systemthat transmits data from the IC card 12 to the main unit 11. FIG. 14 isa timing chart of the system shown in FIG. 13. Next, with reference toFIGS. 13 and 14, the data transmission of the system will be described.

[0077] As shown in FIG. 13, when the data communication is performedfrom the IC card 12 to the main unit 11, the data signal is transmittedfrom the flip-flop FF2S to the flip-flop FF1R. The clock signal of theflip-flop FF1R has a delay that is the sum of a delay due to the outputbuffer CK2S, a delay due to the transmission path CLK, and a delay dueto the input buffer CK1R against the clock signal of the flip-flop FF2S.The sum of the delays is denoted by clock delay TD11.

[0078] In addition, the delay after the timing of a leading edge of theclock input of the flip-flop FF1R until the arrival of the clock signalto the data input of the flip-flop FF2S is the sum of a delay due to theflip-flop FF2S, a delay due to the output buffer 102S, a delay due tothe transmission path DATA, and a delay due to the input buffer 101R.The delay due to the flip-flop FF2S is denoted by data delay TD13. Thesum of the delay due to the output buffer 102S, the delay due to thetransmission path DATA, and the delay due to the input buffer 101R isdenoted by data delay TD12.

[0079] When the four output buffers 102S, CK2S, 101R, and CK1R are ofthe same type, a connector for the transmission path DATA is the same asa connector for the transmission path CLK, and the length of a cableused for the transmission path DATA is the same as the length of a cableused for the transmission path CLK, the clock delay TD11 becomes nearlythe same as the data delay TD12. As shown in FIG. 14, only the datadelay TD13 causes the timing tolerance to decease. Thus, as shown inFIG. 14, the timing tolerance can be prevented from decreasing. As aresult, the system according to the embodiment can communicate at higherrate than the conventional system.

[0080]FIG. 15 shows a system composed of a main unit 51 and an IC card52 according to another embodiment of the present invention. Theembodiment shown in FIG. 15 is different from the embodiment shown inFIG. 12 in that there are two transmission paths CLK_H and CLK_C for aclock signal. According to the embodiment shown in FIG. 15, although twotransmission paths for a clock signal are used, the clock signal can bebi-directionally communicated without need to dispose a clock generatorin the IC card 52.

[0081] In FIG. 15, reference characters FF1R, FF1S, FF2R, and FF2Srepresent flip-flops. Each of the flip-flops FF1R, FF1S, FF2R, and FF2Shas a data input D and a data output Q. Reference characters 101R, 102R,CK1R, and CK2R represent input buffers. Reference characters 101S, 102S,CK1S, and CK2S represent output buffers. The output buffers 101S and102S are composed of tri-state buffers. Reference characters 1DE and 2DErepresent control signals. The main unit 51 has a clock generator 53. Aclock signal is transmitted from the main unit 51 to the IC card 52through the transmission path CLK_H. In addition, the clock signal istransmitted from the IC card 52 to the main unit 51 through thetransmission path CLK_C. A data signal is bi-directionally transmittedbetween the main unit 51 and the IC card 52 through a transmission pathDATA.

[0082] First of all, the case that a data communication is performedfrom the main unit 51 to the IC card 52 will be described. The controlsignal IDE causes the tri-state buffer 101S to be set to an outputenable state. The control signal 2DE causes the tri-state buffer 102S tobe set to an output high impedance state. As a result, data istransmitted from the flip-flop FF1S to the flip-flop FF2R. The clocksignal is generated by the clock generator 53 of the main unit 51. Theclock signal is input to the clock input of the flip-flop FF2R through apath of (output buffer CK1S→transmission path CLK_H→input buffer CK2R).

[0083] The data signal is output from the flip-flop FF1S insynchronization with a leading edge of the clock signal that is inputfrom the clock generator 53 to the clock input of the flip-flop FF1S.The data signal is input to the data input of the flip-flop FF2R througha path of (output buffer 101S→transmission path DATA→input buffer 102R).The data signal is captured in synchronization with a leading edge ofthe clock input of the flip-flop FF2R.

[0084] Next, the case that a data communication is performed from the ICcard 52 to the main unit 51 will be described. The control signal 1DEcauses the tri-state buffer 101S to be set to an output high impedancestate. The control signal 2DE causes the tri-state buffer 102S to be setto an output enable state. As a result, data is transmitted from theflip-flop FF2S to the flip-flop FF1R. The clock signal is generated bythe clock generator 53 of the main unit 51. The clock signal is input tothe clock input of the flip-flop FF1R through a path of (output bufferCK1S→transmission path CLK_H→input buffer CK2R→output bufferCK2S→transmission path CLK_C→input buffer CK1R).

[0085] The data signal is output from the flip-flop FF2S insynchronization with a leading edge of the clock signal that is inputfrom the clock generator 53 to the clock input of the flip-flop FF2Sthrough a path of (output buffer CK1S→transmission path CLK_H→inputbuffer CK2R). The data signal is input to the data input of theflip-flop FF1R through a path of (output buffer 102S→transmission pathDATA→input buffer 101R). The data signal is captured in synchronizationwith a leading edge of the clock input of the flip-flop FF1R.

[0086]FIG. 16 is a schematic diagram showing the structure of the systemthat performs a data communication from the IC card 52 to the main unit51. Since the timing chart of the system shown in FIG. 16 is the same asthat shown in FIG. 14, the timing chart is omitted.

[0087] As shown in FIG. 16, when a data communication is performed fromthe IC card 52 to the main unit 51, the data signal is transmitted fromthe flip-flop FF2S to the flip-flop FF1R. The clock signal that is inputfrom the clock generator 53 to the clock input of the flip-flop FF2S hasa delay that is the sum of a delay due to the output buffer CK1S, adelay due to the transmission path CLK_H, and a delay due to the inputbuffer CK2R. The sum of the delays is denoted by clock delay TD54. Theclock signal that is input from the input buffer CK2R to the clock inputof the flip-flop FF1R has a delay that is the sum of a delay due to theoutput buffer CK2S, a delay due to the transmission path CLK_C, and adelay due to the input buffer CK1R. The sum of the delays is denoted byclock delay TD51. In addition, a delay after a leading edge of the clockinput of the flip-flop FF2S until the arrival of the clock signal to thedata input of the flip-flop FF2S is the sum of a delay due to theflip-flop FF2S, a delay due to the output buffer 102S, a delay due tothe transmission path DATA, and a delay due to the input buffer 101R.The delay due to the flip-flop FF2S is denoted by data delay TD53. Thesum of the delay due to the output buffer 102S, the delay due to thetransmission data DATA, and the delay due to the input buffer 101R isdenoted by data delay TD52.

[0088] In this case, the delay of the clock signal from the clockgenerator to the clock input of the flip-flop FF2S is TD54. On the otherhand, the delay of the clock signal from the clock generator 53 to theclock input of the flip-flop FF1R is the sum of the delay TD54 and thedelay TD51. As a result, the clock signal of the flip-flop FF2S has thedelay TD51 against the clock signal of the flip-flop FF2S. Since onlythe data delay TD53 causes the timing tolerance to decrease, the systemaccording to the embodiment shown in FIG. 16 can perform a communicationat higher speed than the conventional IC card.

[0089] The present invention is not limited to the forgoing embodiments.In other words, various modifications and ramifications are possiblewithout departing from the scope of the present invention. For example,the present invention can be applied to a parallel communication, notlimited to a serial communication.

[0090] According to the present invention, in addition to-a data signalthat is input and output to and from an IC card in synchronization witha clock signal, a clock signal is output from an IC card. In addition,the present invention is structured so that there is no differencebetween the delay time of the clock signal and the delay time of thedata signal. Thus, a communication of data that is output from the ICcard can be performed at higher speed than the conventional IC card.Thus, a large amount of data can be transmitted in a short time.

1. An IC card removable from a main unit of an apparatus, the IC cardhaving a data terminal and a clock terminal, a clock signal beingcapable of being received from the main unit through the clock terminal,the clock signal being capable of being transmitted from the clockterminal to the main unit.
 2. The IC card as set forth in claim 1,wherein the clock terminal is used in common for receiving andtransmitting the clock signal.
 3. The IC card as set forth in claim 1,wherein the clock terminal is composed of two portions for receiving andtransmitting the clock signal, respectively.
 4. An IC card systemcomposed of a main unit of an apparatus and a removable IC card, the ICcard system comprising: interface means including a data transmissionpath and a clock transmission path, wherein the interface means isconfigured: to transmit a first clock signal from the main unit to theIC card through the clock transmission path and transmit data from themain unit to the IC card in synchronization with the first clock signalthrough the data transmission path and, to transmit a second clocksignal from the IC card to the main unit through the clock transmissionpath and transmit data from the IC card to the main unit through thedata transmission path in synchronization with the second clock signal.5. The IC card system as set forth in claim 4, wherein the clocktransmission path is used in common for the first signal and the secondsignal.
 6. The IC card system as set forth in claim 4, wherein the clocktransmission path for the first clock signal is different from the clocktransmission path for the second clock signal.
 7. The IC card system asset forth in claim 6, wherein the main unit has clock generating means,and wherein the first and second clock signals are generated by theclock generating means.